Vertical transistors with gate connection grid
US11652027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Mar 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0297
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.