Via contact patterning method to increase edge placement error margin

US11652045B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mohit K. HARAN · Hillsboro, US
• Daniel James Bahr · Portland, US
• Deepak S. Rao · Portland, US
• Marvin Young Paik · Portland, US
• Seungdo An · Portland, US
• Debashish Basu · Beaverton, US
• Kilhyun Bang · Portland, US
• Jason W. Klaus · Portland, US
• Reken Patel · Portland, US
• Charles H. Wallace · Portland, US
• James Jeong · Beaverton, US
• Ruth A. Brain · Portland, US

Key dates

• Filing date: Oct 27, 2021
• Grant date: May 16, 2023
• Expiry date: Oct 27, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/5329
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.