Disaggregated die interconnection with on-silicon cavity bridge

US11652057B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Khang Choong Yong · Puchong, MY
• Eng Huat Goh · Air Itam, MY
• Min Suet Lim · Kampung Bukit Kechil, MY
• Robert L. Sankman · Phoenix, US
• Telesphor Kamgaing · Chandler, US
• Wil Choon Song · Bayan Lepas, MY
• Boon Ping Koh · Permatang Janggus, MY

Key dates

• Filing date: May 7, 2019
• Grant date: May 16, 2023
• Expiry date: Sep 12, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.