Methods of forming substrate interconnect structures for enhanced thin seed conduction

US11652067B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Christopher J. Jezewski · Portland, US
• Radek P. Chalupa · Portland, US
• Flavio Griggio · Portland, US
• Inane Meric · Hillsboro, US
• Jiun-Chan Yang · Portland, US

Key dates

• Filing date: Dec 28, 2016
• Grant date: May 16, 2023
• Expiry date: Aug 10, 2037

Classification

• Technology area (CPC C): Chemistry; Metallurgy
• CPC primary: C23C18/38
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.