Epitaxy regions with large landing areas for contact plugs
US11652105B2 · kind B2 · utility
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2References
20Claims
0Family size
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Key dates
| Filing date | Jan 7, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Jan 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.