Method of fabricating metal gate transistor
US11652154B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Aug 15, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Aug 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.