Techniques for error detection and correction in a memory system
US11656937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2021 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Aug 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.