Multi-phase topology synthesis of a network-on-chip (NoC)
US11657203B2 · kind B2 · utility
1Cited by
40References
10Claims
0Family size
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Key dates
| Filing date | Dec 9, 2020 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Nov 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC. The process takes a set of constraints as inputs and produces a NoC with all its elements configured and a placement of such elements on the floorplan of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.