Testing bit write operation to a memory array in integrated circuits
US11657887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2021 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Sep 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.