Resistive random-access memory cell and associated cell array structure
US11663455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2020 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Nov 5, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.