Instruction distribution in an array of neural network cores

US11663461B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hartmut Penner · San Jose, US
• Dharmendra S. Modha · San Jose, US
• John V. Arthur · Mountain View, US
• Andrew S. Cassidy · San Jose, US
• Rathinakumar Appuswamy · San Jose, US
• Pallab Datta · San Jose, US
• Steven K. Esser · San Jose, US
• Myron D. Flickner · San Jose, US
• Jennifer Klamo · San Jose, US
• Jun Sawada · Austin, US
• Brian Taba · Cupertino, US

Key dates

• Filing date: Jul 5, 2018
• Grant date: May 30, 2023
• Expiry date: Jan 11, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N5/046
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Instruction distribution in an array of neural network cores is provided. In various embodiments, a neural inference chip is initialized with core microcode. The chip comprises a plurality of neural cores. The core microcode is executable by the neural cores to execute a tensor operation of a neural network. The core microcode is distributed to the plurality of neural cores via an on-chip network. The core microcode is executed synchronously by the plurality of neural cores to compute a neural network layer.