Three-dimensional memory device and manufacturing method thereof
US11665905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2021 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Jul 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.