Sequential delay enabler timer circuit for low voltage operation for SRAMs
US11670361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Jul 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.