Patent · US Active

Multi-tier memory architecture

US11670363B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Rahul Mathur · Austin, US
Mudit Bhargava · Austin, US
Andy Wangkun Chen · Austin, US

Key dates

Filing date	Apr 23, 2021
Grant date	Jun 6, 2023
Priority date	—
Expiry date	Apr 23, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.