High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory

US11672124B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Wei-Cheng Wu · Hengshan, TW
• Ya-Chen Kao · Taoyuan, TW
• Yi Hsien Lu · Yuanchang, TW

Key dates

• Filing date: Feb 25, 2021
• Grant date: Jun 6, 2023
• Expiry date: Jun 3, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.