Separation of plasma suppression and wafer edge to improve edge film thickness uniformity
US11674226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2020 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Feb 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/332
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A chamber for use in implementing a deposition process includes a pedestal for supporting a semiconductor wafer. A silicon ring is disposed over the pedestal and surrounds the semiconductor wafer. The silicon ring has a ring thickness that approximates a semiconductor wafer thickness. The silicon ring has an annular width that extends a process zone defined over the semiconductor wafer to an extended process zone that is defined over the semiconductor wafer and the silicon ring. A confinement ring defined from a dielectric material is disposed over the pedestal and surrounds the silicon ring. A showerhead having a central showerhead area and an extended showerhead area is also included. The central showerhead area is substantially disposed over the semiconductor wafer and the silicon ring. The extended showerhead area is substantially disposed over the confinement ring. The annular width of the silicon ring enlarges a surface area of the semiconductor wafer that is exposed and shifts non-uniformity effects of deposition materials over the semiconductor wafer from an edge of the semiconductor wafer to an outer edge of the silicon ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.