Systems and methods for centralized address capture circuitry
US11675541B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Dec 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a centralized command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types, such as a write command and a read command. The centralized command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.