Embedded packaging for high voltage, high temperature operation of power semiconductor devices
US11676899B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2020 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | May 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ≤5×10−13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ≥75 C, EaLow is ≤0.2 eV and EaHigh is ≤1 eV, for improved reliability for high voltage, high temperature operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.