Semiconductor substrate and method of sawing the same
US11676914B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.