Using error correction code (ECC) bits for retaining victim cache lines in a cache block in a cache memory
US11681620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2021 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Jul 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.