Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training
US11682445B2 · kind B2 · utility
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Key dates
| Filing date | Nov 15, 2021 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Nov 15, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.