Semiconductor device assembly with graded modulus underfill and associated methods and systems
US11682563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2022 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Jun 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/92125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.