Package structure and manufacturing method thereof
US11682612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2021 |
| Grant date | Jun 20, 2023 |
| Priority date | — |
| Expiry date | Apr 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.