Error check and scrub for semiconductor memory device
US11687410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2022 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jan 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.