Localized stress regions for three-dimension chiplet formation
US11688642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Sep 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/3192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.