Core cavity noise isolation structure for use in chip packages
US11688675B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2021 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jun 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/6622
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing circuitry formed in the top build-up layers by vias formed through the core region. A void is formed in the bottom build-up layers. The void is configured as a noise isolation structure. The void has a sectional area that is different in at least two different distances from the core region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.