Flash and fabricating method of the same
US11690220B2 · kind B2 · utility
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9References
9Claims
0Family size
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Key dates
| Filing date | Jul 12, 2022 |
| Grant date | Jun 27, 2023 |
| Priority date | — |
| Expiry date | Jul 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/68
Abstract
A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The sharp angle connects to the first concave surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.