Tunable and scalable command/address protocol for non-volatile memory
US11693794B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 31, 2020 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Oct 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.