Hybrid fine line spacing architecture for bump pitch scaling
US11694898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2019 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Oct 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.