Quality of service control of logical devices for a memory sub-system
US11698876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2022 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Apr 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory sub-system receives a plurality of requests to perform a plurality of input/output (IO) operations corresponding to a plurality of logical devices associated with a memory device and assigns the plurality of requests to respective queues associated with the plurality of logic devices. The processing device further iteratively processes the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.