Simulating memory cell sensing for testing sensing circuitry
US11699502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2021 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Dec 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.