Semiconductor device with resistance reduction element and method for fabricating the same
US11699734B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Feb 10, 2021 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Jun 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin, a gate structure positioned on the fin, impurity regions positioned on two sides of the fin, contacts positioned on the impurity regions, and conductive covering layers positioned on the contacts. The conductive covering layers are formed of copper germanide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.