Low-k feature formation processes and structures formed thereby
US11705327B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2022 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Apr 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.