Fully aligned via integration with selective catalyzed vapor phase grown materials
US11705363B2 · kind B2 · utility
0Cited by
6References
16Claims
0Family size
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Key dates
| Filing date | May 21, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Dec 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.