Vias for package substrates

US11705389B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Andrew J. Brown · Brier, US
• Luke Garner · Chandler, US
• Liwei Cheng · Chandler, US
• Lauren A. Link · Mesa, US
• Cheng Xu · Chandler, US
• Ying Wang · Taichung, TW
• Bin Zou · Chandler, US
• Chong Zhang · Chandler, US

Key dates

• Filing date: Jun 11, 2019
• Grant date: Jul 18, 2023
• Expiry date: Nov 14, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/145
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.