Apparatuses and methods for organizing data in a memory device
US11710524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Aug 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.