Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same
US11710667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2020 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Jul 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.