System and method for scalable hardware-coherent memory nodes
US11714755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2020 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jul 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.