Latch bit cells
US11715514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jun 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.