Transistor gate structures and methods of forming the same
US11715762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Apr 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.