Patent · US Active

Three-dimensional memory devices having through stair contacts and methods for forming the same

US11716846B2 · kind B2 · utility

1Cited by
7References
20Claims
0Family size

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Key dates

Filing dateNov 13, 2020
Grant dateAug 1, 2023
Priority date—
Expiry dateMay 19, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/10
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.