Semiconductor package and method of manufacturing the same
US11721601B2 · kind B2 · utility
0Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2020 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Mar 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.