Fabrication method of fin transistor
US11721702B2 · kind B2 · utility
0Cited by
6References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 20, 2022 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Jun 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.