Laterally diffused metal oxide semiconductor with gate poly contact within source window
US11721738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Mar 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.