Dynamic power and thermal loading in a chiplet-based system
US11722138B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Aug 14, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A chiplet system comprises an interposer including interconnect and multiple chiplets arranged on the interposer and interconnected using the interconnect of the interposer. The multiple chiplets include a throttle level bus source chiplet including a throttle level bus drive interface configured to place a throttle level value onto the throttle level bus, and one or more throttle level bus receiver chiplets operatively coupled to the throttle level bus. Each chiplet of the multiple chiplets includes throttling logic circuitry configured to set a throttle level of a chiplet according to the throttle level value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.