Strained transistors and phase change memory
US11723220B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Feb 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.