Methods of reducing clock domain crossing timing violations, and related devices and systems
US11727979B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Jul 7, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Aug 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.