Integrated planar-trench gate power MOSFET
US11728423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.