Write training in memory devices by adjusting delays based on data patterns
US11733887B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | May 11, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Jul 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.