Variable width superblock addressing
US11740819B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Sep 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.